FPGA application case in HD low-stream video coding

Overview

The resolution and code stream of the security camera are positively related. After entering the high-definition era, the code stream is above 2Mbps, which is more than 3 times higher than the previous D1 era. Such a large code stream is transmitted in the local network of 100M/1000M. The problem, the cost of hard disk storage is also acceptable; but if you want to transmit high-definition video on the Internet and 3G networks, the low-stream requirements are highlighted.

The first is the problem of uploading high-definition video to the Internet. At present, the most popular and cheapest uploading technology is ADSL. The upload speed is 512Kbps, and it can be uploaded with 3G. The upload speed of CDMA2000 is 1.8Mbps, due to the theoretical peak and actual continuous average of wireless transmission. There is a considerable gap in the value, so it can be estimated within a few hundred Kbps; secondly, the problem of downloading high-definition video from the Internet to the display terminal, the download speed of ADSL can generally be above 4Mbps, and downloading one tens of tens from the Internet at home using 3G. For MB files, the download speed of TD-SCDMA is about 430Kbps, the download speed of CDMA2000 is about 720Kbps, and the download speed of WCDMA is about 1120Kbps.

In summary, if high-definition video is to be easily and economically applied on the Internet and 3G networks, an average stream of 512 Kbps is suitable. There is still a problem in the application of high-definition video in the Internet and 3G networks, that is, the fluctuation of the real-time bandwidth of the network is relatively large. The lower the average code stream of the video transmitted in this environment, the more assured the quality of the video.

The current status quo is that the video stream of HD video 720p is generally above 2 Mbps, and the code stream of 1080p is above 4 Mbps. To greatly reduce the code stream, it needs to be considered from several aspects.

H.264 encoder and FPGA

Video compression coding is the most effective way to reduce the code stream. Currently, H.264 is the preferred standard for encoders. The H.264 encoding algorithm is complex and uses many methods to reduce the code stream. In general, a video consists of consecutive frames, and the encoded frames mainly have I frames, P frames, and B frames. The encoding of the I frame does not depend on other frames, and only uses the pixels in the frame to perform various predictions to reduce the encoded code stream; the P frame uses the current frame and the previous frame as a reference, and uses various pixels in the frame and pixels between the frames to perform various types. Predicting to reduce the coded stream; B-frames use the current, previous, and subsequent frames for reference, and use the pixels within the frame and the pixels between the frames to make various predictions to reduce the coded stream.

From a practical point of view, P-frames and B-frames have the greatest contribution to reducing the coded stream, because in the monitoring application, the ratio of P-frames and B-frames to I-frames can be large; and the effect of B-frames is more obvious: not only can be utilized The reference frame is used to increase the accuracy of the prediction, and the decoding result of the B frame may not be used as the reference frame, so that the coded stream can be reduced by appropriately reducing the B-frame coding quality, so that the code stream of the B frame can be compared with the P frame. a lot less. The B frame is the same as the P frame except that the P frame is more backward than the P frame. Therefore, we only consider the I frame and the P frame, and discuss the quantization of the FPGA in the prediction and transformation results. The role played.

Prediction - the advantages of FPGA in parallel processing

The prediction method adopted by the I frame is relatively simple, and can be adopted in both P frame and B frame, so all prediction methods of the I frame should be implemented all; the prediction method of the P frame is very complicated, and the H.264 encoder is large. Part of the workload is here. The prediction purpose of the P frame is to find the position of the current macroblock in the reference frame (the macroblock can be divided into several parts to match), and the matching precision is 1/4 pixel, and the exact matching can minimize the encoding.

In order to reduce the workload, the search matching of integer pixels is generally performed first, and then the final matching of 1/2 and 1/4 pixels. To improve the success rate of search matching, the number of reference frames, the search range and the number of matches are all Very critical. In general, a large number of reference frames or a large search range requires a relatively large number of matches.

Due to the hardware real-time and pipeline requirements, the prediction of P-frames must be completed in a fixed unit time. In order to achieve as many matching times as possible in a short period of time, parallel processing is the only choice, and FPGAs are processed in parallel. The superiority is demonstrated, and the matching of multiple positions at the same time can be realized. Like some small diamonds of 4 points or 3 points matching, the SAD of 3 to 4 points can be calculated at the same time, which is 3 to 4 times faster than the point-by-point calculation. In addition, multiple reference frames can also be processed in parallel, while obtaining the minimum SAD of different reference frames; parallel processing can greatly improve the number of matches, but also requires a large amount of internal memory and logic resources, which needs to be considered from the overall resources of the entire design.

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