Abstract: HDB3 code has no DC component, and has clock recovery and good anti-interference ability. This article proposes the use of HDB3 code for high-speed long-distance data transmission, and gives the use of single-chip AT89C51 control E1 transceiver chip DS2153Q to achieve NRZ-HDB3 code conversion, including code converter circuit design and control software design. Keywords: NRZ HDB3 MCU E1 transceiver chip DS2153Q The commonly used NRZ code is not suitable for transmission in the channel of high-speed long-distance data communication, so another code—HDB3 code is selected. HDB3 code is an important coding method for serial data transmission. Compared with the most commonly used NRZ code, HDB3 has many advantages, such as: eliminating the DC component of the NRZ code, with better anti-jamming performance of clock recovery, which makes it more suitable for long-distance channel transmission. E1 signal adopts HDB3 coding method, the rate is 2.048Mbps, and it can transmit 1.5km on RJ45 balanced twisted pair with characteristic impedance of 120Ω, which can meet the high-speed long-distance transmission of data in most cases. When the data rate is less than 2.048Mbps, the data rate can be increased by inserting additional data bits. The E1 transceiver chip DS2153Q fully complies with the E1 signal standard, and has a peripheral microcontroller interface, which greatly improves the usability of the chip. E1 has three methods: framing, multiframing and unframing. In the framed E1, the 0th time slot is used to transmit frame synchronization data, and the remaining 31 time slots can be used to transmit valid data; in the multiframe E1, except for the 0th time slot, the 16th time slot is For signaling, only the 1st to 15th, 17th to 31st total 30 time slots can be used to transmit valid data; and in the unframed E1, all 32 time slots can be used to transmit valid data. The E1 of the NRZHDB3 code converter proposed in this paper works in unframed mode, which means that the 32 time slots of E1 are all used to transmit valid data. DS2153Q is a T1 / E1 transceiver chip from Dallas, which complies with the latest E1 line standards, including ITU G.703, G.704, G.706, G.823, I.431, ETSI300 011, 300 233, TBR12 and TBR13, etc. The chip can complete the conversion between NRZ and HDB3 codes, the code rate can reach 2.048Mb / s, and the circuit will be restored when the data of the NRZ code is integrated in the chip, which is more conducive to the subsequent receiving circuit. The on-chip D / A can realize the output waveform of G.703 standard, suitable for the twisted pair of 75Ω and 120Ω characteristic impedance, and has a complete data flow status monitoring function, which can indicate the transmission status of the data flow in real time. The peripheral microcontroller interface of DS2153Q makes it easy to interface with MCUs such as microcontrollers. The 71 internal 8-bit registers enable users to configure and monitor the DS2135Q through the MCU. These registers mainly include the receive control register, the transmit control register general control register, the interrupt mask register and the working status register. Figure 1 shows the internal structure of the DS2135Q. Figure. NRZ-DB3 code system converter is the conversion of NRZ code to HDB3 code and HDB3 code to NRZ code. The design uses special E1 receiving chip DS2153Q and single chip AT89C51 to realize the conversion function of the code system. The code system converter converts the input NRZ to HDB3 code output, and at the same time converts the data on the E1 line into HRZ code, and restores the data clock for the later-stage data receiving unit. AT89C51 is an 8-bit single-chip microcomputer from Atmel, responsible for controlling the working mode and status monitoring of the communication chip DS2153Q, so that it can complete the conversion from NRZ code to HDB3 code and HDB3 code to HRZ code. At the same time, the peripheral circuit of the microcontroller also includes the μP monitoring circuit IMP813L, which is used to improve the anti-interference ability and reliability of the code converter. Figure 2 is a block diagram of the code converter. The parallel data / address line of the DS2153Q is connected to the P0 port of the microcontroller; the chip selection signal is selected from the P2.0 of the microcontroller; the read and write signal of the microcontroller is connected to the read and write signal of the DS2153Q; at the same time, the two interrupt application lines of the DS2153 are connected to the INT0 of the microcontroller Connect to INT1. In this way, the DS2153Q can notify the working state of the microcontroller in a timely manner through interrupts. The circuit connection diagram of AT89C51 and DS2153Q is shown in Figure 3. Through the above hard connection, the single-chip microcomputer controls and monitors the DS2153Q. In the circuit design of DS2153Q, in order to make it work in unframed mode, all the transmitted data is input from the TSER pin, and the pins TLINK and TSER need to be shorted. The light-emitting diode is used for the work instruction of the converter, and can intuitively judge whether the current data conversion is normal. The code converter uses RJ45 balanced twisted pair with a characteristic impedance of 120Ω for data transmission. The DS2153Q transceiver circuit is shown in Figure 4. The input-output turns ratio of the transmission transformer is 1: 1.36. 3 SCM control program design The converter single-chip control program includes two parts: DS2153Q function configuration and DS2153Q working status monitoring. The function configuration of DS2153Q realizes the normal operation of HDB3 code; DS2153Q working status monitoring is used to obtain whether the current converter is working normally in real time, and report and indicate in time. 3.1 DS2153Q function configuration After the converter is powered on, it is first effectively reset by the μP monitoring circuit to ensure the normal initialization of the single-chip microcomputer, and a single-chip microcomputer enters the configuration process of the communication chip DS2153Q. ①Initialize the test register and write 0 to the corresponding test register. ② Configure the receiving control register (RCR), including receiving frame mode, automatic resynchronization enable, resynchronization criterion and receiving dynamic storage function, etc., so that DS2153Q receiving single chip works in Auto Resync, Disable ElasTIc Store. ③ Configure the transmission control register (TCR), including the transmission frame mode, automatically set the fault bit and the function selection of the 16-bit pin, etc., so that the DS2153Q transmission unit works in E-bits not automaTIcally set in the transmit direcTIon, and according to The different settings of the current conversion mode set the 16-pin function, 0 = Receive Loss of Sync (RLOS), 1 = Loss of Transmit Clock (LOTC). ④ Configure the common control register (CCR), enable the reception and transmission of DS2153Q and HDB3 codes, configure the update time of the error counter, and prohibit the dynamic storage of transmission data. ⑤ Initialize the interrupt mask register, enable receive carrier loss, receive out-of-step interrupt, receive data all 0 and all 1 interrupts, enable transmit clock lost interrupts, through these interrupts, the microcontroller can be informed of the working state of DS2153Q in time Its implementation is monitored. ⑦Initialize the transmission line interface control register, including transmission waveform selection, receiver equalizer gain selection, anti-jitter suppression selection, etc. The single-chip microcomputer control flow is shown in Figure 5. The following is the function configuration program (part) of DS2153Q. ; ************************************************* ****; MOV A, 02H MOV DPTR, # RCR1 MOVX @DPTR, A; write register RCR1, enable automatic resynchronization NOP MOV A, # 04H MOV DPTR, # RCR2 MOVX @DPTR, A; write register RCR2, disable flexible storage function NOP MOV A, # 41H MOV DPTR, # TCR1 MOVX @DPTR, A; write register TCR1, TSYNC is the output mode NOP MOV A, # 0F9H MOV DPTR, # TCR2 MOVX @DPTR, A; write register TCR2, E data bit is forbidden to set automatically NOP MOV A, # 44H MOV DPTR, # CCR1 MOVX @DPTR, A; write register CCR1, allowing receiving and sending NOP; HDB3 code NOV A, # 00H MOV DPTR, # CCR2 MOVX @DPTR, A; write register CCR2, configure error count register NOP ; ************************************************* ******* 3.2 DS2153Q state monitoring design After completing the DS2153Q register configuration, the single-chip microcomputer enters the transmission status monitoring program to monitor whether the DS2153Q is working normally in real time, including reading the status register and the DS2153Q interrupt response, and judging faults and reporting in time. (1) Send status monitoring The sending status monitoring of DS2153Q is realized by INT1 of the single chip microcomputer. When the send status bit of the status register is set to 1, the DS2153Q generates an interrupt, and the slicer reads the fault bit of the current status register in response to the interrupt. When the reading is completed, you need to write 1 to the specific status bit of the status register to ensure that future faults can be set correctly. The following gives the status monitoring program (interrupt 1 handler) of the NRZ transmit clock loss fault. MOV DPTR, # SR2; read DS2153Q status register 2 NOP MOVX A, @DPTR ANL A, # 04H JNZ ERROR SJMP FAVER ERROR: SETB ERR_SR SJMP LOCKE FAVER: CLR ERR_SR LOCKE: JNB ERR_SR, WORK; judge whether the sending data clock is lost SETB P1.0; fault, work indicator diode off SJMP EVER WORK: CLR P1.0; normal, work indicator diode is on EVER: MOV DPTR, # SR2 MOV A, # 04H MOVX @DPTR, A RETI (2) Receive status monitoring The receiving status monitoring of DS2153Q is realized by INT0 of the single chip microcomputer. When the sending status bit of the status register is 1, the DS2153Q generates an interrupt, and the microcontroller reads the fault bit of the current status register in response to the interrupt. When the reading is completed, you need to write 1 to the specific status bit of the status register to ensure that future faults can be set correctly. The following gives the status monitoring program (interrupt 0 handler) of the HDB3 code receiving carrier loss failure. MOV DPTR, # SR1; read DS2153Q status register 21 NOP MOVX A, @DPTR ANL A, # 02H JNZ ERROR SJMP FAVER EPPOR: SETB ERR_SR SJMP LOCKE FAVER: CLR ERR_SR LOCKE: JNB ERR_SR, WORK; determine whether the received carrier is lost SETB P1.0; fault, work indicator diode off SJMP EVER WORK: CLR P1.0; normal, work indicator diode is on EVER: MOV DPTR, # SR1 MOV A, # 02H MOVX @DPTR, A RETI 4 Summary The NRZ-DB3 code converter uses the E1 transceiver chip DS2153Q to complete the conversion of NRZ code to HDB3 code and HDB3 code to NRZ code, to achieve high-speed long-distance data transmission, so that the 2.048Mb / s data stream is twisted pair on the RJ45 interface It achieves a transmission distance of 1.5km to meet most high-speed data transmission situations. Led Ceiling Lamp,Modern Ceiling Lamps,Led Recessed Ceiling Lights,Remote Control Ceiling Lights Changxing Fanya Lighting Co.,Ltd , https://www.fyledlights.com
1 Brief introduction of E2 transceiver chip DS2153Q 
2 Code converter circuit design
Figure 3 AT89C51 and DS2153Q circuit connection diagram
The code converter uses IMP813L as the μP monitoring circuit to achieve reliable power-on reset and watchdog control. The clock signal of DS2153Q is realized by dividing the clock signal of the microcontroller by two. The one-chip computer chooses the clock signal of 16.384MHz, uses 74HC74 two frequency division, get 8.192MHz frequency signal as DS2153Q input clock. 
â‘¥ Initialize the transmission line interface unit, write 0 to LIRST data bit, and then write 1 to make the transmission line interface enter the normal working mode. 