Low noise, high linearity 3.5GHz LNA design

The sensitivity of the wireless receiver is actually mainly related to the system noise figure (F), because the bandwidth (BW) is predetermined by the standard.

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(Formula 1)

A low-noise amplifier (LNA), as its name implies, improves receiver sensitivity by reducing the system noise figure. The Friss formula shows that the noise figure (F1) of the receiver's first-stage circuit dominates, and the influence of the latter-stage circuit (ie, F2, F3 ...) gradually decreases.

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(Formula 2)

Among them, Gn represents the gain of the nth stage circuit in the receiving link.

The transmitter and the receiver share a single antenna through a frequency selective duplexer, or a frequency domain duplex or time domain duplex (TDD) radio frequency switch. In addition, a band-pass filter may be inserted before the LNA to prevent it from being blocked or desensitized by strong out-of-band interference. Unfortunately, both the duplexer and the filter are passive devices, and there is some RF loss. Because these losses occur before the LNA, they have a large impact on the overall sensitivity. Therefore, if the LNA noise figure has a certain design margin, the loss specifications of the duplexer and filter may be less important.

In addition to low noise, other important performance parameters include gain and linearity. The wireless infrastructure usually includes an LNA installed on the top of the tower. This LNA needs to be connected to a radio cabin on the ground through a long cable. Therefore, in order to overcome cable losses, it is best to have a higher gain. The linearity is important because the RF spectrum around the tower is very crowded, because the base station is shared with other wireless services.

The purpose of this article is to show that, from a performance and cost perspective, a single-stage GaAs PHEMT microwave monolithic integrated circuit (MMIC) is the best solution for 3.5GHz LNA used in wireless infrastructure.

MMIC device

Figure 1 shows the internal and external circuits of Avago ’s MGA-635P8 MMIC. The internal circuit consists of a cascode amplifier (AMP) and an active bias regulator (BIAS) fabricated on the same die. The cascode topology is mainly designed according to the requirement of greater than 15dB gain at 3.5GHz, because the common source (CS) design using the same GaAs enhanced pseudomorphic high electron mobility transistor (ePHEMT) process can only reach 13dB gain. Although the two-stage cascode circuit can achieve the desired gain by cascading, the cascode topology has the additional advantage of current reuse, that is, the same current flows through the two-stage circuit.

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Figure 1: (a) LNA circuit and (b) PCB and components.

In some receiver implementations, when the input signal is very strong, the gain stage circuit after the LNA will be bypassed by the RF switch. The change in LNA load matching (ΓL) caused by the switching will be passed back to the input matching (S11) because the device is non-unidirectional (ie S12 ≠ 0). Both the antenna and the input filter are very sensitive to termination, and they may be detuned due to S11 changes. When S12 is close to zero, S11's sensitivity to load changes will decrease, (Equation 21) (when s12 → 0).

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The reverse isolation of the cascode topology is 1/200 to 1/2000 of the cascode topology, which is the second reason for choosing the cascode topology. Because the direct conversion receiver is more sensitive to the local oscillator's self-mixing, this device can also benefit from better isolation.

Each FET in the cascode topology can only get half of the total supply voltage Vdd. Therefore, in low-voltage operation, the gain and linearity of the cascode topology may be lower than the cascode topology. EPHEMT is an ideal choice for cascode, because its gain and linearity are very stable when Vds ≥ 2V. The cascode output should be cascaded with the series RC network in order to improve the stability above the operating frequency.

MMIC is manufactured using a mature and cost-effective 0.25μm process, and its gain bandwidth product fT exceeds 30GHz. In addition to minimizing the number of circuit stages required to achieve the target gain, a higher fT is also conducive to achieving a low noise figure. In addition, by doubling the thickness of the metal, Johnson noise generated in the circuit interconnection can be minimized. This 0.64x0.64mm chip is installed in an 8-pin square flat no-lead (QFN, 2x2x0.75mm) plastic package.

The internal bias regulator allows the LNA quiescent current (Ids) to be controlled via RBIAS or externally applied bias voltage VBIAS. The regulator's low current drive requirements (IBIAS≤1mA) are compatible with most CMOS devices, and can use 5V logic switching LNAs in time-domain duplex (TDD) applications (disconnecting the LNA can prevent the gate current from increasing during transmission. Metal migration). The device threshold voltage (VT), forward transconductance (gm) and RDS (conduction) will change with temperature and wafer, and then reverse the operating point. In this design, integrating a bias regulator and LNA on one chip helps to stabilize the operating point, because the VBIAS and VGS voltages can "mirror" each other to compensate for thermal drift and gm changes between different wafer batches .

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