Abstract : Embedded real-time image processing technology is a cutting-edge technology that combines image processing, pattern recognition, sensors and microelectronics. Embedded real-time image processing is also possible, driven by the rapid development of electronic technology. Under the current electronic technology conditions, the author combined with DSP technology, CPLD/FPGA technology, image processing technology, sensor technology, etc., developed a practical embedded real-time image processing system - industrial smart camera, realized the product Automatic detection and classification of quality. This article refers to the address: http:// 0, introduction: In industrial production, the degree of automation of production equipment largely determines the efficiency of production. At the same time, high-tech high-tech production equipment has a great effect on improving the grade of products. At the industrial production site, there is a lot of work that is repeated with simple labor, or the working environment is not suitable for people to deal with. At this point, you can design a smart instrument that can be used to perform this simple repetitive work or work in a harsh working environment. A smart camera system is such an automated instrument. It is increasingly valued by industrial production for its high efficiency, stable performance, and adaptability to complex and harsh working environments. This article will introduce a design of a smart camera for quality control of industrial production sites, and give the actual work of the camera. 1 , the overall design of the system: For the camera system design, the primary consideration is the matching between the production speed of the industrial field and the processing speed of the camera. The overall design of the system must be based on the amount of data that needs to be processed to select the type of processor required, the operating speed of the peripheral interface components, and the type and parameters of the selected sensor. Industrial production speed is generally calculated as how many products per minute, and must be converted to seconds. Combining various factors, in the design of this smart camera system, the image sensor adopts CMOS monochrome VGA format image sensor LM9617 produced by National Semiconductor, and the logic control and address generator of the system are produced by LATTICE. CPLD ispLSI1048C, the central processing unit uses the high-speed digital signal processor TMS320VC5402 from Texas Instruments, and the display device adopts the liquid crystal display PD064VT5 produced by Taiwan Yuantai Company. LVDS level shifting is used between the sensor and the image buffer to improve transmission and interference immunity over long distance transmissions. After selecting the working components of each part of the system, the overall structural design of the system is shown in Figure 1. Figure 1 Schematic diagram of the overall structure of the system       The image data output by the sensor and the control signal to the sensor are level-transformed by LVDS and sent to the CPLD logic buffer control unit and sensor, respectively. Under the control of the DSP, the CPLD completes the buffering and transmission of images and the configuration of the sensors. The central processing unit DSP processes the cached image, and after completion, writes the processed result image to the display cache. When the processing result is written, the display of the processing result image is completed by the display drive controller. 2 , system parts and function description: (1) Image sensor unit: The image sensor mainly performs conversion of the optical information signal to the electrical signal to obtain image information. Considering the working conditions of ordinary industrial production lines, in this system, the image sensor adopts CMOS monochrome VGA format image sensor LM9617 produced by National Semiconductor, and its working voltage is 3.3V, and the effective pixel is 648×. 488, pixel size can be Figure 2 LM9617 pin and typical application circuit As can be seen from the typical application circuit diagram, the peripheral circuit of the sensor is simple, and only a small number of RC components can complete the design of the sensor circuit. Its control and register configuration is also simple and convenient through the sensor's camera control pins and serial bus (IC) control pins. (b), logic and control unit: Since the amount of image data generated by the sensor is large, the amount of data generated per second is 648 × 488 × 30 Byte. Considering the processing speed of the central processing unit DSPVC5402, it is decided to adopt a two-way buffering and branching processing technique for the image. When performing image buffering, CPLD is used to implement address generator and logic control functions. In this system, the address generator and logic control unit are implemented using the large-scale complex programmable logic device ispLSI1048C manufactured by LATTICE. The ispLSI1048C has 8000 logic gates, 96 I/O ports, 12 dedicated input ports, four clock input ports, 288 registers and 48 GLB units inside, and its working clock can reach 50MHz. When caching, the address and data isolation of the memory are implemented by 1048C. At the same time, when the DSP reads data from the buffer, the isolation of the data signal and the address signal is also implemented by 1048C. In addition, the read and write control logic of the cache channel is completed by the 1048C under the control of the DSP, and the data cache communication with the DSP is realized. The design of this part is shown in Figure 3: Figure 3 Schematic diagram of the logic control unit structure After the system is powered on, the DSP sends a write image command to the 1048C. After receiving the command, the 1048C first determines whether a frame image arrives according to the field signal, and then generates an address according to the pixel clock and the line signal to buffer the image. When an image is buffered, an image buffer completion signal is sent to the DSP. After the DSP receives the image buffer, on the one hand, the control 1048C continues to buffer the next frame image, and on the other hand, the cached image is detected. (3) Central processing unit: The central processing unit is the core part of the system, which involves issues such as system efficiency and stability. After considering the processing speed, data volume, control complexity, system design complexity, algorithm complexity and system cost of the system, this paper selects the high-speed digital signal processor TMS320VC5402 produced by Texas Instruments (TI) as the central processing. The operating frequency can reach 100MHz, and the command can run up to 100MIPS, which can meet the needs of common digital signal processing. Figure 4 Schematic diagram of the central processing unit structure In the system design, the DSP program is optimized. The program memory uses FLASH AT29LV020 produced by Atmel Company. Its size is 256K×8Bit, and it is loaded in 8Bit parallel loading mode at runtime. At the same time, considering the real-time display of the processing results, and taking into account the display process, the system design uses a 1M × 8Bit display cache. The cache is used as the data buffer of the system. The partial cache is added to the display control part during design. The structure of the central processing unit is shown in Figure 4. (4) Display control unit: The image display portion is completed using a liquid crystal display. The liquid crystal display has the characteristics of stable and reliable, low power consumption, compact structure and rich display content. It is commonly used as a human-machine interface in the development and design of embedded systems and has been widely used. In this system, the grayscale bitmap is to be displayed. According to the actual situation, the gray level of the image is controlled to 256 levels, that is, 8Bit. Since there is no LCD screen that can display 256 gray levels on the market, the system design uses the 6.4' true color LCD screen PD064VT5 produced by Taiwan Yuantai Company with a resolution of 640×480 and a refresh rate of 60Hz. Up to 256K color. In the design, according to the conversion of RGB to YUV, the G channel and the B channel of the liquid crystal panel are connected to the R channel in parallel, and the 64-level grayscale image is displayed. The drive controller is developed by the author and its structure is shown in Figure 5. Figure 5 shows the drive control unit When designing the display drive control circuit, the control and logic generator and address generator unit are still implemented by 1048C, and the frame buffers I and II have a capacity of 512K×8Bit. Frame buffers I and II are used as display buffers during display, and frame buffers I and II are used as data buffers for algorithm processing. The logic control is completed by 1048C. The power section is the more important part of the system. The entire system is powered by a linear power supply. Among them, the sensor is powered by 3.3V, the CPLD1048C is powered by 5V, the DSP is powered by the power module TPS767D301, and the LCD is powered by 5V and 12V. It will not be detailed here. 3 , system implementation: After completing the design of the whole system, we implemented the system and applied the smart camera system to the paper quality monitoring line, mainly to detect the defects or stain spots in the paper. If a flaw is found on the surface of the paper, a paper failure signal is given. When the image processing algorithm is not complicated, the system can work in real time and reach 30FPS. After adding some more complicated processing algorithms, the system can work at 15FPS and convert to industrial production speeds of 900 products per minute. This is fully meet the production needs in general industrial production. Figure 6 shows a typical example of detecting a defective paper after it is applied to the inspection line: (a) original stain image (b) detection algorithm processing result Figure 6 test results       In the test results, the size and position information of the sputum or stain point are given, and according to the actual requirements, the signal of whether the single product is qualified is given. 4. Conclusion: Smart camera is an emerging real-time image research and processing direction in China. It combines real-time image processing, microelectronics technology, sensor theory and many other disciplines. Its design and application have certain difficulty and complexity. However, due to its broad application prospects, it will surely receive more and more attention. This paper presents a more general design scheme of the smart camera and realizes the hardware and software design of the whole system. It has been proved that the scheme is feasible and feasible. The camera system developed according to the scheme works fast and has stable and reliable performance. The actual application has been achieved. references: [1] Data Sheet of: LM9617 Monochrome CMOS Image Sensor VGA 30 FPS. NationalSemiconductor Corporation. March, 2001.
Keywords : DSP CPLD/FPGA image processing smart camera . At a clock frequency of 48 MHz, the output image is 30 FPS. Due to the CMOS process, the output of the sensor is directly the digital signal of the image, and the output image data can be 8 bits, 10 bits or 12 bits. Its control and working mode configuration is done under the control of the DSP through the CP2 and the sensor's I2C bus. The CMOS image sensor is packaged in PLCC48
Its pin definition and typical application circuit are shown in Figure 2:
[2] Data Sheet of: Specifications for ispLSI 1048C. Lattice Semiconductor Corporation. August 2000.a
[3] Data Sheet of: TMS320C54XDSP Cpu & Peripherals. TI. April, 1999.
[4] Data Sheet of: 2-Megabit 3-volt Only Flash Memory AT29LV020. Atmel Corporation. May, 2002
[5] Data Sheet of: Technical Specification Model NO.: PD064VT5. PRIME VIEW INTERNATIONAL CO.,LTD. May, 2004.
[6] Li Gang. The principle of digital signal processor and its development and application. Tianjin: Tianjin University Press. 2000.4.
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