Research on on-chip communication architecture in SoC design For most of the time since the 1970s, the feature size of VLSI devices has shrunk at a rate of 70 9/6 every three years, allowing an increasing number of transistors to be fabricated on the same semiconductor chip . Due to the advantages in speed, price, area, power consumption and time to market, SoC design based on IP core multiplexing technology has gradually become an important field of ultra-large scale integrated circuit design, especially SoC for wireless communication, multimedia and consumer electronics The design of the field provides a better cost-effective integrated solution. In SoC design, the study of on-chip communication is one of the key technologies in the basic research of SoC design at home and abroad. Crossbar (Crossbar) based on-chip communication interconnection structure, including single-level crossbar interconnection and multi-level crossbar interconnection. Literature [11] believes that, in theory, for multiprocessor parallel computing applications, the use of crossbars to communicate, its efficiency is the highest; however, the cost of its implementation is greater. For a crossbar switch with N nodes, its implementation complexity and cost increase with O (N2). In an N × M crossbar network, each processor can read and write different memory modules, and all processors and memory modules can communicate in parallel. When two or more processors request access to the same module, the arbitration mechanism will cause one processor to access while the other processors wait. In recent years, as the feature size of integrated circuit manufacturing has gradually shrunk, the crossbar interconnect structure has also been applied in SoCs. Arbitration sequence: There are N master devices in the SoC, denoted as M1, M2,…, Mi,…, MN (i = 1, 2,…, N), if the i-th master device is arbitrated as Xi , Then the sequence {X1, X2, ..., Xi, ...} is called the arbitration sequence. In Figure 1, it is the crossbar that exchanges data packets. If there is only one or two DSPs in the SoC, the crossbar can have 2M ports; and if there is a processor (DSP) array, the crossbar can have 2M + 1 ports to facilitate a two-dimensional grid Extension. The MUX unit in Figure 1 can use a strobe, as shown in Figure 2. At present, Verilog RTL code has been written for the arbiter, interface unit and on-chip crossbar switch, and the function verification has been carried out under the Cadence simulation environment. The next step is to perform logic synthesis on TSMC's 180 nm low-power standard cell library, and obtain performance parameters such as area, power consumption, and main frequency under Cadence's simulation environment, and complete the design and evaluation of the above-mentioned on-chip communication structure backend. auto relays,12v relay,auto 12v relay,auto start relay,automotive relay Dongguan Andu Electronic Co., Ltd. , https://www.autoido.com
1 Introduction to on-chip communication architecture technology There are five main types of on-chip communication architecture at home and abroad: shared bus structure, on-chip network structure, crossbar switch, point-to-point communication, and mixed on-chip communication structure.
The interconnection method of the shared bus can be divided into: single bus, multi-bus and hierarchical bus. Shared bus-style on-chip communication is mainly developed by the company and widely used in actual SoC design, such as IBM's CoreCon-nect bus interconnection framework, ARM's AMBA bus, and other companies' buses, etc. The school also has research on on-chip communication with a shared bus, such as the Science Foundation project "High-performance SoC asynchronous interconnection technology research" of Xidian University, and the Science Foundation project of Nanjing University "Dynamic reconfigurable SoC: data communication problems Research "etc. The arbiter is one of the key technologies in the shared bus. Existing arbiter priority strategies include static priority strategy, time division multiplex priority strategy and lottery priority strategy based on random numbers. Although the shared bus interconnect structure can be suitable for a large number of applications and adopted, but it also has some problems. First of all, there are various IP modules in the SoC, each module has its own communication requirements, and the usual single bus structure can only authorize a requesting master device to occupy the shared bus at the same time, thus limiting the performance of the entire SoC . At the same time, with the increasing scale of SoC, the problem of long interconnection of the bus structure, the problem of crosstalk under deep submicron technology, and the problem of voltage drop are all manifested.
In recent years, domestic and foreign scholars have proposed the use of computer network interconnection and communication technology for SoC on-chip network design and research. This on-chip network structure can greatly improve the performance of multiprocessor SoCs. However, it is equivalent to the shared bus structure, which also brings greater hardware and delay overhead. In 2002, De Micheli of the University of Standford proposed the use of computer network interconnection technology in SoC design. He believes that the on-chip network can bring higher bandwidth communication links and easily expandable nodes to the SoC. At the same time, using this technology can improve the SoC's quality of service (QoS). For the on-chip network, the current research mainly focuses on the structure, communication protocol, high-level synthesis and design automation of the network on chip (NOC). In recent years, a variety of on-chip network interconnection structures based on message switching networks have been proposed, many of which have been studied, including two-dimensional grid NoC and scalable programmable on-chip network SPIN.
The NextJs SoC chip described in [12] adopts an asynchronous cross-switch interconnection method with 16 ports. Under the 130 nm process, the main frequency is 1.35 GHz, and the equally divided package bandwidth reaches 780 Gb / s. The point-to-point on-chip communication interconnection structure means that each IP core has its own dedicated communication link. Compared with the shared bus, it has unique advantages. For example, the capacitive load of point-to-point communication is relatively small, so there is a small delay. However, since there are communication links between each IP core, its interconnection resources will inevitably increase, resulting in difficulties in placement and routing. Each IP core also requires more communication ports, increasing the chip area. In [13], the author proposed a comprehensive algorithm for point-to-point communication based on power consumption constraints. Against H. The encoder used in 263 is synthesized using this algorithm. Compared with the current synthesis results of traditional sharing, the area overhead on the chip is increased by 4%, but the connection length is reduced by 15%, and the power consumption of the chip is reduced. To the original 26%.
Literature [14] proposed the concept of on-chip communication diversity, that is, using a combination of different on-chip communication structures to divide the entire chip into several islands, each island may use different voltages and clock frequencies to achieve the optimization of specific system parameters Purpose, such as power consumption and throughput. Especially in recent years, the on-chip communication network has made the combination of on-chip communication networks more and more abundant. By combining the above-mentioned various on-chip communication structures, the advantages of various communication methods can be fully utilized. For example, the overhead of the bus method is small, and the data transmission performance that needs to be shared is high, while the on-chip network method can increase the data transmission. Reliability and parallelism, with high communication bandwidth, therefore, the hybrid on-chip communication structure provides a new design space for high-performance SoC design.
Research on the architecture of on-chip communication provides an exploration space for on-chip communication design optimized for performance in SoC. At the same time, the study of specific performance parameters such as power consumption, reliability and bandwidth of the on-chip communication system is also of great significance for the optimized design of on-chip communication.
2 A new on-chip communication architecture According to market predictions, the SoC scale in the global market will exceed the total IC market share in 2010, so the research and design of on-chip communication as one of the key technologies for SoC design is of great significance. Based on the research of on-chip communication architecture at home and abroad, a hybrid on-chip communication structure combining a shared bus and an on-chip network is proposed. Figure 1 shows a schematic diagram of a 2-channel hybrid on-chip communication structure. This hybrid on-chip communication architecture combines a traditional on-chip shared bus with an on-chip network. In this way, for an SoC with N master and slave IP cores, M channels can be configured to communicate in parallel.
The arbiter in Figure 1 is used to arbitrate the communication applications and authorizations of all modules. A priority model based on application and authorization is proposed here. 
Arbitration cycle sequence segment: If the arbitration cycle is L (positive integer), then the i-th arbitration cycle sequence segment is: 
Mi to Mj authorization transfer: If Xi is Mi and Xi + 1 is Mi, then {Xi, Xi + 1} is called Mi to Mj authorization transfer.
Authorization mode: In the i-th arbitration cycle sequence segment {X (i-1) × L + 1, X (i-1) × L + 2,…, X (i-1) × L + L} (i = In 1, 2, ...), if the authorization number of the j-th master device is recorded as nj (j = 1, 2, ..., N), then {n1, n2, ..., nj, ..., nN} is called the i-th The authorization mode of an arbitration cycle sequence.
From the definition of authorization mode and arbitration period, we can get: 
Generally, in a certain running time period, the priority of each IP core in the SoC will be different from another running time period. Therefore, the priority of each IP core in the SoC must have time locality. Under this premise, using the authorization mode in the sequence segment of the i-th arbitration cycle stored, Xi × L + j = Mk (k = 1, 2, ..., N) the probability of Mi ~ Mj's authorized transfer. 
3 Conclusion It has been verified that the optimized architecture of on-chip communication not only retains the advantages of a small shared bus area on-chip, but also has the advantages of parallel communication on-chip network. At present, the on-chip communication IP core with optimized architecture has been used in actual SoC design. In the future, the research results will have important practical applications in the design of high-definition digital TV processor SoC chips, 3G wireless mobile terminal baseband SoC chips, and other SoC chips that have or will be developed in China.