The workload of chip verification accounts for about 70% of the entire chip development, which has become a bottleneck for shortening the time to market. Applying OVM methodology to build a DMA IP verification platform in SoC design can effectively improve verification efficiency. With the development of integrated circuit design to a very large scale, the difficulty of chip verification work is increasing, and the verification workload has accounted for about 70% of the entire SoC research and development. Chip verification directly affects the time of chip launch, thus improving chip verification. Efficiency has become crucial. By using the characteristics of OVM's hierarchical and random constraints, it can effectively improve the existing verification methods, improve the level of environmental incentives and monitoring, and speed up the coverage to achieve the process, thus speeding up the verification. OVM verification platform OVM is a completely open validation methodology jointly developed by Mentor Graphics and Cadence Design System, dedicated to providing design and verification engineers with an abstraction-level verification environment. OVM provides a rich library class and advanced verification technology to enable the verification platform to be reused from the module level to the system level, and can be run on the policy verification platform of multiple manufacturers. The OVM verification platform adopts a hierarchical structure and is divided into five layers, namely DUT, transport layer, OperaTIonal, analysis layer and control layer. The bottom layer is the DUT, which is the IP or SoC design with a Pin-level interface that needs to be verified. Above the DUT level is the transport layer, which is used to connect the Pin level DUT to the transport layer. All components above the transport layer are components based on the transaction transport layer. The introduction of the transaction transport layer can make the design of the verification environment get rid of the constraints of the actual DUT signal interface, and make the transmission of the upper layer information more efficient and faster. From the transport layer, each layer is composed of different transaction components. For example, the analysis layer is composed of coverage collection, performance analysis, scoreboard, reference model, etc. All components at different levels interact to form a hierarchical layer. A verification environment that can be reused. In the baseband SoC chip, the DMA module is responsible for data movement in the SoC system. The module has an AHB Master interface and an AHB Slave interface, wherein the AHB Slave interface is used for CPU to configure DMA functions, and the AHB Master interface is responsible for data reading. With the write, the FIFO is set in the module to buffer the DMA interaction data. The basic components in the OVM verification platform generally include driver, sequencer, sequence, monitor, instantiate these components in ovm_agent, multiple ovm_agent instantiated in ovm_env, and in order to achieve self-contrast mechanism, need to instantiate scoreboard in ovm_env, Finally, instantiate ovm_env in the component of type ovm_test and specify the sequence corresponding to the sequencer of each agent in the environment. The components in the OVM environment are connected to each other through a transport layer interface, and the data transmitted in this transport layer interface is transmitted. OVM has defined the transport layer interface, we only need to instantiate it. Transmitting data is an abstraction of the physical interface (ie, IP interface). After abstracting the IP interface, it uses the components in the OVM for high-level processing. The IP has two interfaces, one is the standard AHB Master interface, and the other is the standard AHB Slave interface. Two types of transmission data need to be defined for these two interfaces. OVM extends the ovm_transacTIon class to define the transmission data we need. Supports the use of the systemverilog constraint mechanism to perform randomization constraints on the above two types of transmission data. For example, according to the IP specification, hsize can be restricted to 2'b00~2'b10 in ahbm_pkt, and addr is 32'h0000_0000~32'hFFFF_FFFF randomly. In order to evaluate the verification effect, it is necessary to collect the function coverage. The part of the code is in the scoreboard, and the systemverilog covergroup is used to collect the verified function points. After constructing modular and reusable verification components by borrowing transaction transactions and interfaces, use the class library of each component to create random excitations and sequences, and convert the excitation and sequence into DUT interface behaviors; use assertions, scoreboards, etc. to judge DUT behavior. Correctness; at the same time collect and analyze information such as functional coverage and code coverage. In the process of verification, we control the variables of the input excitation and increase the error injection information to ensure that the system correctly reflects in the wrong state. Validation at increasingly higher levels of abstraction is a major trend in current validation methodology. By building an OVM-based hierarchical IP verification platform, all the functions of the baseband SoC chip DMA IP are verified and 100% functional verification coverage is achieved. The OVM verification method only needs to extend or reuse the components in the hierarchical architecture, which greatly improves the verification efficiency of the SoC chip, thereby shortening the development cycle of the entire project. The project has been successfully streamped.
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